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Design flow

The ASIC design flow is a highly automated approach applying state-of-the-art submicron design methodologies such as early floor planning, links-to-layout, timing driven placement and routing. The first time right claim is backed by design-for-test measures such as full scan design, ATPG (Automatic Test Pattern Generation), BIST (Built-in Self Test), IDDQ testing etc.

Tight time-to-market cycles are met by using advanced verification methods such as static timing analysis, formal verification and well defined sign-off procedures for all techologies. For the various design steps we use industry leading, commercially available tools.

We ensure continuous learning on design-flow and technology and implement regular updates of our design system and libraries based on latest silicon results.

Our design team sums up more than 250 years of expierience in development of mixed-signal ICs for high-voltage applications that are used in industrial, medical, IT or automotive environments.

IC Design Tools:

  • Synopsys
  • Mentor Graphics
  • Cadence

Additional Tools:

  • Altium Designer
  • FPGA (Xilinx, Altera)
  • Micro controller software development



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